| Formation Connectivity - S-FPDP |
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You are here: ac6 > ac6-formation > Connectivity > S-FPDP |
| IS1 | S-FPDP |
| Objectives | |||
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The course details the hardware implementation of S-FPDP and clarifies the operation of 8b10b encoder/decoder. |
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Transfer sequences captured with the Absolut-Analysis equipment are studied to explain the frame formats and the flow control mechanism. |
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The course describes the parameterizing of the Xilinx S-FPDP IP based on Multi Gigabit transceiver integrated in Virtex FPGAs. |
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| A more detailed course description is available on request at info@ac6-training.com | |||
| Prerequisites | |||
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Basic knowledge on serial buses. | ||
| Outline |
| INTRODUCTION | |||
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Benefits of S-FPDP with regard to other high-speed interconnects | ||
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Layered protocol | ||
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Allowed bit-rates and distances | ||
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Copper vs optic fiber media | ||
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Point-to-point protocol | ||
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Relationship with FibreChannel | ||
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Introduction to FibreChannel low layers | ||
| CONVERTING PARALLEL-FPDP SIGNALING INTO S-FPDP SIGNALING | |||
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Overview of P-FPDP | ||
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Strobe signals | ||
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Frame delimitation | ||
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Flow control | ||
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Data frame types | ||
| S-FPDP SYSTEM SPECIFICATIONS | |||
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Basic systems, no feedback channel | ||
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Flow control, related ordered sets, FIFO management | ||
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Taking into account the cable length | ||
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Bi-directional data flow | ||
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Copy mode, multicast emulation, options for re-transmitting the clock | ||
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Copy / loop mode, benefit of a feedback channel to enable flow control | ||
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Error recovery | ||
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Exercice : studying traces captured by the Absolut-Analysis equipment to understand the flow control mechanism | ||
| LINK SPECIFICATIONS | |||
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Typical S-FPDP process | ||
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Understanding 8b10b coding scheme | ||
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Runtime DC balance through disparity calculation | ||
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Requirements for clocks | ||
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Avoiding underrun and overrun, using an elastic buffer | ||
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List of ordered sets | ||
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Electrical characteristics | ||
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Fiber frame types | ||
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Exercice : studying traces captured by the Absolut-Analysis equipment | ||
| XILINX S-FPFP IP | |||
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MGT block diagram | ||
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Parameterizing the MGT to support S-FPDP | ||
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CoreGen | ||
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Focus on the analog part of the transceiver | ||
| Duration | Cost | Calendar |
| 2 days | 1250 € |
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